Capacitive pressure difference sensor, and manufacturing method and application thereof

ABSTRACT

Provided are a pressure difference sensor, and a manufacturing method and an application thereof. A manner of bonding three layers of wafers is adopted, and the sensor includes an upper structure, an intermediate structure and a lower structure. Each of the upper structure and the intermediate structure is manufactured by a silicon-on-insulator (SOI) wafer, the lower structure is manufactured by patterned doped intrinsic silicon; and a lead pad of each of the upper electrode, and the intermediate electrode and the lower electrode is located on a corresponding one of three-stepped steps at a side of the pressure difference sensor. Annular through holes are formed around the upper electrode and the lower electrode. A constant capacitance of a capacitance signal outputted by an upper capacitor of the sensor by extending an electric field line path of the constant capacitor part.

TECHNICAL FIELD

The present disclosure relates to a sensor, and in particularly to a capacitive pressure difference sensor, and a manufacturing method and an application thereof, and belongs to a design field of an electronic component.

BACKGROUND

A pressure difference sensor is used in industrial measurement technology to measure a pressure difference between two separated cavities on the pressure difference sensor. A Micro-Electro-Mechanical Systems (MEMS) pressure difference sensor made by MEMS technology means that THE MEMS pressure difference sensor can be made of a wafer compound using a well-known MEMS semiconductor technology.

The pressure difference sensor has an intermediate-layer movable diaphragm arranged between two matrixes in a common manner. The intermediate-layer movable diaphragm and each of the two matrixes are enclosed to together to form two pressure cavities. In a measurement process, one pressure cavity at one side of the intermediate-layer movable diaphragm is loaded with a first pressure, the other pressure cavity at the other side of the intermediate-layer movable diaphragm is loaded with a second pressure, and a pressure difference between the two pressure cavities makes the intermediate-layer movable diaphragm shift to a side thereof with a weak pressure.

In the capacitive pressure difference sensor, a top portion and a bottom portion of the capacitive pressure difference sensor form an upper electrode and a lower electrode respectively, and the intermediate-layer movable diaphragm is located between the upper electrode and the lower electrode. The upper electrode and the lower electrode respectively form two capacitors with the intermediate-layer movable diaphragm. The shifting of the intermediate-layer movable diaphragm makes a spacing between the intermediate-layer movable diaphragm and an electrode with a weak pressure side decrease and makes a spacing between the intermediate-layer movable diaphragm and an electrode with a strong pressure increase. Correspondingly, one of capacitances of two capacitors on both sides of the intermediate-layer movable diaphragm becomes larger, and the other becomes smaller, which results in a capacitance difference, thus completing a conversion from a pressure difference signal to a capacitance difference signal.

Each of the upper capacitor and the lower capacitor of the capacitive pressure difference sensor includes two parts. Take the upper capacitor C_(upper) (as shown in FIG. 1 ) as an example, one of the two parts is a capacitor C_(upper) variable (also referred to as a variable upper capacitor), which is variable with the shifting of the intermediate-layer movable diaphragm, and the other of the two parts is a capacitor C_(upper) constant (also referred to as a constant upper capacitor), which is not variable with the shifting of the intermediate-layer movable diaphragm. Based on this, an electric field line may also be divided into two parts, one of the two parts is an electric field line path corresponding to the variable upper capacitor, and the other of the two parts is an electric field line path corresponding to the constant variable upper capacitor.

In an actual measurement process, a capacitance change percentage of the upper capacitor is ΔC_(upper variable)/(C_(upper variable)+C_(upper constant)), and a capacitance change percentage of the lower capacitor is similar to it. When a constant capacitor is too large, a proportion of a variable capacitor to a total capacitor of the upper capacitor is smaller, and a measurement accuracy is smaller. Therefore, during device design, it is necessary to improve a proportion of the variable capacitor to the total capacitor through materials and structures. For example, through reducing a cross-sectional area through which an electric field line of the constant capacitor can pass and extending the electric field line path of the constant capacitor, a capacitance value of the constant capacitor can be reduced and the proportion of the variable capacitor to the total capacitor can be increased.

For an existing capacitive pressure difference sensor, a silicon capacitive pressure difference sensor with a Fuji brand of Japan, as a representative, mostly adopts a multi-layer matrix structure, with doped silicon as upper and lower electrodes and an intermediate-layer movable diaphragm. Specifically, silicon conductive layers are separated by an insulating layer such as ceramics and an oxide layer, and conduction of electrodes often needs to pass through the insulating layers using for example through-hole sputtering or metal plating. Further, an external circuit lead from a side wall of the sensor, and a pressure guide hole is often located directly above and below a center of the intermediate-layer movable diaphragm. In an actual semiconductor sensor processing process, in order to facilitate cutting and reduce the cost, the sensor is often processed into a square. In the practical work of the existing capacitive pressure difference sensor, under the coordination of an anti-overload structure, the intermediate-layer movable diaphragm will not shift too much and will not contact with the upper and lower electrodes.

At present, the capacitive pressure difference sensor in the related art has at least the following defects.

An intermediate-layer movable diaphragm of the existing capacitive pressure difference sensor should be symmetrical on both sides, a thickness and smoothness of the intermediate-layer movable diaphragm should be taken into account, and the cleanliness and smoothness of a bonding surface should also be taken into account, therefore, a structure of the intermediate-layer movable diaphragm should not be too complicated, and an intermediate island structure and an ordinary flat film are often used. Based on a current structural design, the capacitive pressure difference sensor has to sacrifice more linearity, sensitivity or resolution. For a general intermediate island film, the shifting of the general intermediate island film mainly depends on an island film, which has a higher linearity, but has a lower sensitivity. For a common flat film with a higher sensitivity, its nonlinearity is higher, and the sensitivity decreases with the increase of a pressure difference, which makes it difficult to read and calibrate a signal.

The pressure guide holes of upper and lower electrode plates of the existing capacitive pressure difference sensor are often located directly above and below the center of the intermediate-layer movable diaphragm. When an over-range pressure difference signal is input, the intermediate-layer movable diaphragm of the sensor is easy to shift excessively, thereby blocking the pressure guide holes, and thus resulting in structural failure of the sensor. Therefore, in an actual packaging process, in order to avoid pressure overload, it is necessary to add an additional anti-overload structure, which makes a whole package structure of the sensor too large, so that it is not suitable for application in a small space.

For a constant capacitor of the existing pressure difference sensor, various products and patents have made efforts. For the capacitive pressure difference sensor with the Fuji brand of Japan, doped silicon is used as upper, intermediate and lower electrodes, and a thick ceramic layer is used as an insulating layer of a bonding portion of between the upper electrode and the intermediate electrode, which ensures that a spacing between the intermediate-layer movable diaphragm and the each of the upper and lower electrode plates is within tens of microns, and also prolongs the electric field line path of the constant capacitor, thereby reducing the constant capacitor. This design uses thick ceramics and thick silicon wafers for bonding, which greatly increases a dimension of the sensor. In Chinese patent No. CN 106471350A, doped silicon is used as each electrode and silicon dioxide is used as an insulating layer, and a groove is formed by etching the intermediate-layer movable diaphragm, a vacuum region is formed between the electrodes, which can reduce the constant capacitor. However, because a bonding area is determined by an actual process, it is difficult to substantially reduce a cross-sectional area through which an electric field line of the constant capacitor can pass, and each of a spacing between electrode plates at the bonding portion and a spacing between electrode plates at the intermediate-layer movable diaphragm is a thickness (several hundred nanometers to two or three microns) of a silicon dioxide layer, so it is difficult to actually reduce the constant capacitor too much.

A lead of the pressure difference sensor can be divided into two parts, one of the two parts is used to lead an electrode inside the pressure cavity to a surface of the sensor (called an internal lead), and the other of the two parts is used to lead the surface of the sensor to a signal reading circuit (called an external lead). A common manner for arranging the lead includes sputtering conductive metal and using doped silicon. For the capacitive pressure difference sensor with the Fuji brand of Japan, the internal lead of the upper and lower electrodes thereof is arranged through metal sputtering, and passes through the insulating layer made of ceramic, which realizes electrical communication between the upper and lower electrodes (doped silicon layer) in the cavity and external upper and lower cover plates (doped silicon layer). However, for the external lead of the capacitive pressure difference sensor with the Fuji brand of Japan, the lead passes through a side wall of a conductive layer of the sensor, which makes it difficult to integrate and package the sensor.

Most existing capacitive pressure difference sensors adopt silicon-silicon direct bonding or anode bonding to realize the air tightness of the cavity. The d silicon-silicon direct bonding requires high technological conditions such as a bonding temperature, a pressure and a surface flatness, and the process is difficult. For the anodic bonding, a thermal stress caused by mismatch of thermal expansion coefficients of silicon and glass is greatly reduced. While metal eutectic bonding can meet the requirements of the air tightness, a process thereof is simpler and a thermal stress is relatively small, which is more conducive to the bonding of a three-layer complex structure and the manufacturing of a three-layer capacitive pressure difference sensor.

SUMMARY

The present disclosure aims to provide a capacitive pressure difference sensor with a higher sensitivity (an intermediate-layer movable diaphragm can contact upper and lower constant electrodes without blocking a pressure guide hole, and a capacitance value can be adjusted by changing a spacing between capacitor plates and a contact area between the capacitor plates), a higher resolution (a smaller proportion of a constant capacitance value and a larger proportion of a variable capacitance), a wider linear output range, a stronger overload protection ability (bearing a pressure value 2 to 200 times of a full-scale), and a simpler lead manner (the electrode plates lead from a side wall of a pressure cavity to a surface of the sensor and connects to an external circuit from a side of the sensor), and a manufacturing method of the capacitive pressure difference sensor.

The technical solutions of the present disclosure are as follows.

A pressure difference sensor in provided according an embodiment of the present disclosure, which is manufactured by a manner of bonding three layers of wafers, and including: an upper structure, an intermediate structure and a lower structure; where each of the upper structure and the intermediate structure is manufactured by a silicon-on-insulator (SOI) wafer, and the lower structure is manufactured by patterned doped intrinsic silicon; where an upper electrode, an intermediate electrode and a lower electrode are respectively arranged on the upper structure, the middle structure and the lower structure, and a lead pad of each of the upper electrode, the intermediate electrode and the lower electrode is located on a corresponding one of three-stepped steps at a side of the pressure difference sensor; and where annular through holes are formed around the upper electrode and the lower electrode.

Preferably, the pressure difference sensor is made by cutting the three layers of wafers after bonding of the three layers of wafers, and a manner of the bonding is metal eutectic bonding; the metal eutectic bonding includes an upper metal bonding layer and a lower metal bonding layer, an upper portion of the upper metal bonding layer comes from an upper wafer and a lower portion of the upper metal bonding layer comes from an intermediate wafer; and an upper portion of the lower metal bonding layer comes from an intermediate wafer and a lower portion of the lower metal bonding layer comes from a lower wafer.

Preferably, the upper electrode is located in the upper structure, and is formed by processing the upper wafer; the intermediate electrode is located in the intermediate layer structure, and is formed by processing the intermediate wafer; and the lower electrode is located in the lower structure.

Preferably, a pressure guide hole in the upper structure and a pressure guide hole in the lower structure are arranged to be surround the upper electrode and the lower electrode respectively.

Preferably, the upper structure is made by processing the SOI wafer, an upper silicon part of the SOI wafer is intrinsic silicon with a high resistivity, an intermediate layer of the SOI wafer is silicon oxide, a lower silicon part of the SOI wafer is heavily doped silicon, and the upper electrode is derived from the heavily doped silicon of the lower silicon part of the SOI wafer;

the intermediate structure is made by processing the SOI wafer, an upper silicon part of the SOI wafer is intrinsic silicon with a high resistivity, an intermediate layer of the SOI wafer is silicon oxide, a lower silicon part of the SOI wafer is heavily doped silicon, and the intermediate electrode is derived from the heavily doped silicon of the lower silicon part of the SOI wafer; and the lead pad of the intermediate electrode is configured to connect the intermediate electrode to an external circuit; and

the lower structure is made by processing an intrinsic silicon wafer with a high resistivity, the lower electrode is made through patterned doping of the wafer, a circular portion of a doped part mainly plays the role of a capacitor plate, a bottom rectangle portion of the doped part is configured to make ohmic contact with the lead pad of the lower electrode, and a portion between the circular portion and the bottom rectangle portion is a lead portion, which is responsible for realizing the electrical connection between the circular portion and the bottom rectangle portion.

Preferably, a spacing between the lower electrode and the intermediate electrode is composed of three parts including: silicon dioxide having supporting and insulating functions on a lower surface of the intermediate structure, the lower metal bonding layer, and silicon dioxide having supporting and insulating functions on an upper surface of the lower structure; a thickness of the silicon dioxide having supporting and insulating functions on the lower surface of the intermediate structure is in a range from 0 to 3 μm, a thickness of the lower metal bonding layer is in a range from 0 to 4 μm, a thickness of the silicon dioxide having supporting and insulating functions on the upper surface of the lower structure is in a range from 0 to 3 μm, and a sum of the three thicknesses is no more than m.

A manufacturing method of a sensor including the above pressure difference sensor is provided according to an embodiment of the present disclosure, where the method includes process flows for manufacturing the upper structure, the intermediate structure and the lower structure;

where the process flow for manufacturing the upper structure includes:

step 1, etching the pressure guide hole, a lead hole, an upper step hole, aligning marks and cutting marks located in the upper structure;

step 2, performing etching a lower surface to form a boss to prepare for manufacturing the upper electrode;

step 3, removing a silicon dioxide layer exposed after etching the lower surface;

step 4, forming an insulating silicon dioxide layer on a surface of the wafer, that is, the silicon dioxide having supporting and insulating functions on the lower surface of the intermediate structure, and the silicon dioxide having supporting and insulating functions on the upper surface of the lower structure;

step 5, exposing the upper electrode on the upper surface to prepare for a consequent lead;

step 6, preparing for manufacturing a portion of the upper metal bonding layer located in the upper structure; and

step 7, manufacturing the portion of the upper metal bonding layer located in the upper structure;

where the process flow for manufacturing the intermediate structure includes:

step 1, forming silicon dioxide on a surface to: prepare for forming silicon dioxide having supporting and insulating functions on the lower surface of the intermediate structure and silicon dioxide having supporting and insulating functions on the upper surface of an intermediate structure; and prepare for forming a portion of the upper metal bonding layer located in the intermediate structure, a portion of the lower metal bonding layer located in the intermediate structure, and the lead pad of the lower electrode;

step 2, removing silicon dioxide on a surface of a portion to be etched;

step 3, forming a cutting hole and the intermediate-layer movable diaphragm; and

step 4, removing the photoresist;

where the process flow for manufacturing the lower structure includes:

step 1: forming the lower electrode;

step 2: forming silicon dioxide on a surface of the lower structure to prepare for the subsequent processing, and reducing a roughness of the surface and improving a flatness of the surface;

step 3: forming the pressure guide hole in the lower structure to expose the lower electrode;

step 4, forming a silicon dioxide insulating layer on an exposed surface of the lower electrode;

step 5, exposing doped silicon under the lead pad of the lower electrode;

step 6, sputtering metal to prepare for forming a portion of the lower metal bonding layer located in the lower structure and the lead pad of the lower electrode; and

step 7: forming a portion of the lower metal bonding layer located in the lower surface and the lead pad 25 of the lower electrode.

A design method of a Micro-Electro-Mechanical Systems (MEMS) contact capacitive pressure difference sensor, including the pressure difference sensor according to claim 1, and the method including:

(1) for a patterned constant electrode and a lead circuit thereof manufactured by a doping process, using ion implantation used to complete deep doping of a high dose and a high voltage for the electrode; after that, completing wet oxidation and planarization of a silicon wafer, and partially corroding a silicon oxide layer to expose a patterned part of the electrode; where the reason for the planarization operation is that an oxidation rate of a doped part is higher, resulting in a surface of the silicon oxide layer of the doped part being slightly higher than that of an undoped part, and a flatness of the whole wafer exceeds the requirement for the bonding; and

(2) etching and cutting upper, intermediate and lower layers of bonded silicon wafers to form grooves respectively, where sensor areas of the three bonded silicon wafers have a same width, and a length increases from top to bottom of the three bonded silicon wafers by tens to hundreds of microns; and after covering the pressure guide hole with a mask, cutting the sensor into a rectangle and form a three-layer lead step.

The present disclosure has at least the following beneficial effects.

The electric field lines (a potential change path) of a constant capacitor part of the upper capacitor and a constant capacitor part of the lower capacitor of the sensor of the present disclosure is relatively longer (as shown in FIG. 1 ), and intrinsic silicon with a high resistivity (indicated by the reference numerals 3, 23 and 31 in FIG. 2 ) and silicon dioxide with a high resistivity and a relatively small dielectric constant (indicated by the reference numerals 15, 27 and 31 in FIG. 2 ) are used in the electric field line path, which makes the constant capacitors relatively small and a resistivity of the sensor greatly improved.

The present disclosure realizes the measurement of a fluid pressure difference in two different cavities by picking up the variation of two capacitors. A measuring film will shift to the side with a smaller pressure, a spacing between the measuring film and the electrode with the weak pressure will be reduced, a capacitor at the side with the smaller pressure will increase, and the capacitor at the side with a greater pressure will decrease. When the pressure difference further increases, the spacing between the intermediate-layer movable diaphragm and the electrode at the side with the smaller pressure will be further reduced until the intermediate-layer movable diaphragm is in contact with the electrode at the side with the smaller pressure. Further, the distance between the intermediate-layer movable diaphragm and the electrode at the side with the smaller pressure is equal to a thickness of an insulating layer, and with the increase of the pressure difference, the contact area will gradually increase, the capacitor at the side with the smaller pressure will further increase, the capacitor at the side with the greater pressure will further decrease, and the output sensitivity, resolution and linearity of the sensor will be improved.

When the pressure difference is overloaded, the intermediate-layer movable diaphragm will be attached to the side with the smaller pressure, and the electrode at the side with the smaller pressure will support and protect the intermediate-layer movable diaphragm.

External lead pads of the sensor are arranged at the three steps, and an external circuit is electrically connected with to the lead pads at the three steps of the sensor, which is convenient for the integration and packaging of the sensor.

BRIEF DESCRIPTION OF DRAWINGS

In order to more clearly explain embodiments of the present disclosure or the technical solution in the related art, accompanying drawings which are required in the description of the embodiments or the related art will be briefly introduced hereinafter. It is apparent that the accompanying drawings in the following description are merely some embodiments of the present disclosure, and for ordinary technicians in the field, other drawings can be obtained based on these accompanying drawings without creative labor.

FIG. 1 illustrates a schematic view for explaining a distribution of capacitors of a capacitive pressure difference sensor according to an embodiment of the present disclosure.

FIG. 2 illustrates a schematic structural view of a sensor of an MEMS capacitive pressure difference sensor according to an embodiment of the present disclosure.

FIG. 3 illustrates a corresponding explanation of each legend according to an embodiment of the present disclosure.

FIG. 4 illustrates a schematic view of a manufacturing process of an upper structure of a pressure difference sensor according to an embodiment of the present disclosure.

FIG. 5 illustrates a top view of the upper structure according to the embodiment of the present disclosure after being processed in step 4.

FIG. 6 illustrates a bottom view of the upper structure according to the embodiment of the present disclosure after being processed in step 7.

FIG. 7 illustrates a schematic view of a manufacturing process of an intermediate structure of the pressure difference sensor according to an embodiment of the present disclosure.

FIG. 8 illustrates a top view of the intermediate structure according to an embodiment of the present disclosure after being processed in step 4.

FIG. 9 illustrates a schematic view of a manufacturing process of a lower structure of the pressure difference sensor according to an embodiment of the present disclosure.

FIG. 10 illustrates a top view of the lower structure according to the embodiment of the present disclosure after being processed in step 1.

FIG. 11 illustrates a top view of the lower structure according to the embodiment of the present disclosure after being processed in step 5.

FIG. 12 illustrates a top view of the lower structure according to the embodiment of the present disclosure after being processed in step 9.

FIG. 13 illustrates a schematic view of a three-layer structure after three-layer wafer bonding is completed according to the embodiment of the present disclosure.

FIG. 14 illustrates a schematic view of magnetron sputtering of an upper electrode lead pad and a lower electrode lead pad after three-layer wafer bonding is completed according to the embodiment of the present disclosure.

FIG. 15 illustrates a schematic view of a cutting method after three-layer wafer bonding is completed according to the embodiment of the present disclosure.

FIG. 16 illustrates a top view of an independent pressure difference sensor after cutting is completed according to the embodiment of the present disclosure.

REFERENCE NUMERALS

-   -   1—pressure guide hole located in an upper structure;     -   3—intrinsic silicon portion of a silicon-on-insulator (SOI)         wafer used for manufacturing an upper structure;     -   5—metal eutectic bonding portion (upper metal bonding layer)         between an upper structure and an intermediate structure;     -   7—silicon dioxide insulation layer on a surface of an upper         electrode;     -   9—intermediate silicon dioxide portion of an SOI wafer used for         manufacturing an intermediate structure;     -   11—intermediate electrode;     -   13—metal eutectic bonding portion (lower metal bonding layer)         between an intermediate structure and a lower structure;     -   15—silicon dioxide having supporting and insulating functions on         an upper surface of a lower structure;     -   17—silicon dioxide insulation layer on a surface of a lower         electrode;     -   19—lower electrode (a heavily doped part of substrate silicon);     -   21—pressure guide hole located in a lower structure;     -   23—intrinsic silicon portion of a lower structure;     -   25—lead pad of a lower electrode;     -   27—silicon dioxide having supporting and insulating functions on         a lower surface of an intermediate structure;     -   29—lead pad of an intermediate electrode;     -   31—intrinsic silicon portion of an SOI wafer used for         manufacturing an intermediate structure;     -   33—silicon dioxide having supporting and insulating functions on         an upper surface of an intermediate structure;     -   35—silicon dioxide having supporting and insulating functions on         a lower surface of an upper structure;     -   37—lead pad of an upper electrode;     -   39—upper electrode;     -   41—intermediate silicon dioxide portion of an SOI wafer used for         manufacturing an upper structure;     -   43—intermediate-layer movable diaphragm (a movable portion of an         intermediate electrode); and     -   45—silicon dioxide having an insulating function on an upper         surface of an upper structure.

DETAILED DESCRIPTION OF EMBODIMENTS

In order to make objectives, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly described with reference to the accompanying drawings. It is apparent that the described embodiments are a part but not whole of embodiments of the present disclosure. Based on the described embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the art without creative labor belong to the scope of protection of the present disclosure.

First Embodiment

A design solution of a capacitive pressure difference sensor is as follows.

(1) A working principle of the capacitive pressure difference sensor is differential capacitors, and the sensor has three layers of electrodes including an upper electrode, an intermediate electrode, and a lower electrode, which are located in an upper structure, an intermediate structure and a lower structure respectively. The upper electrode 39 is located in the upper structure, the intermediate electrode 11 is located in the intermediate structure, and the lower electrode 19 is located in the lower structure. The intermediate electrode 11 and the upper electrode 39 together form an upper capacitor, and the intermediate electrode 11 and the lower electrode 19 together form a low capacitor. A pressure difference between two sides of an intermediate-layer movable diaphragm 43 located in the intermediate electrode 11 causes the intermediate-layer movable diaphragm 43 to deform and shift, thereby causing the upper capacitor and the lower capacitor to change, and then a signal can be output. The change of the upper capacitor and the lower capacitor can be divided into three stages, including: when the pressure difference between the two sides is smaller, a spacing between the intermediate electrode and each of the upper and lower electrodes has only changed, but the intermediate electrode is not in contact with any one of the upper and lower electrodes; when the pressure difference between the two sides increases to a certain extent, the intermediate electrode is in contact with an electrode with a smaller pressure, and a spacing between the contacted two electrodes is a constant value, i.e., a thickness of a silicon dioxide insulation layer, since the thickness is very small, a capacitor between the contacted two electrodes is much larger than that of uncontacted two electrodes; and when the pressure difference between the two sides continues to increase, a contact area between the intermediate electrode and an electrode with a greater pressure increases, which can be explained as an opposite area of the electrodes increases. Based on this working principle, linearity, sensitivity and overload resistance of the pressure difference sensor will be improved.

(2) The sensor is made through bounding and then cutting three layers of wafers. A manner of the bonding is metal eutectic bonding. In a design solution of this embodiment, Aurum-Tin eutectic bonding is adopted. Similarly, copper-tin eutectic bonding may also be adopted. The reason why the metal eutectic bonding is used is that it has better air tightness and a smaller bonding area, a temperature required for the bonding is smaller, the requirement on a roughness of a bonding interface is lower, and a thermal stress of the device is smaller. Metal eutectic bonding layers can be represented using the reference numerals 5 and 13 in FIG. 2 , where the reference numeral 5 refers to a metal eutectic bonding portion (upper metal bonding layer) between the upper structure and the lower structure, that is, a connection portion between an upper wafer and an intermediate wafer; and the reference numeral 13 refers to a metal eutectic bonding portion (lower metal bonding layer) between the intermediate structure and the lower structure, that is, a connection portion between the intermediate wafer and a lower wafer. In order to obtain the metal eutectic bonding portion 5 between the upper structure and the intermediate structure, it is necessary to sputter metal in advance for corresponding parts of the upper wafer and the intermediate wafer, that is to say, an upper portion of the metal eutectic bonding portion between the upper structure and the lower structure indicated by the reference numeral 5 in FIG. 2 comes from the upper wafer and a lower portion thereof comes from the intermediate wafer. Similarly, an upper portion of the metal eutectic bonding portion between the upper structure and the lower structure indicated by the reference numeral 13 comes from the intermediate wafer, and a lower portion thereof comes from the lower wafer.

(3) The upper electrode 39 is located in the upper structure (reference numerals 1, 3, 7, 35, 37, 39, 41, 43, and the upper portion of the upper metal bonding layer indicated by the reference numeral 5 shown in FIG. 2 ), and the upper structure is formed by processing the upper wafer. The intermediate electrode 11 is located in the intermediate structure (reference numerals 9, 11, 27, 29, 31, 33, the lower portion of the upper metal bonding layer indicated by the reference numeral 5 and the upper portion of the lower metal bonding layer indicated by the reference numeral 13 shown in FIG. 2 ), and the intermediate structure is formed by processing the intermediate wafer. The lower electrode 19 is located in the lower structure (reference numerals 15, 17, 19, 21, 23, 25 and the lower portion of the lower metal bonding layer indicated by the reference numeral 13 shown in FIG. 2 ).

(4) Reference numerals 7 and 17 in FIG. 2 respectively refer to a silicon dioxide insulation layer on a surface of the upper electrode and a silicon dioxide insulation layer on a surface of the lower electrode, which are used to prevent the capacitors from breakdown and failure when the electrodes are in contact, and play the role of insulation layers.

(5) Reference numerals 1 and 21 in FIG. 2 respectively refer to a pressure guide hole located in the upper structure and a pressure guide hole located in the lower structure. The two pressure guide holes surround the upper electrode (indicated by the reference numeral 39 in FIG. 2 ) and the lower electrode 19 respectively. A position distribution of the pressure guide hole located in the upper structure indicated by the reference numeral 1 in FIG. 2 is shown in blank parts of FIG. 5 . A position distribution of the pressure guide hole located in the lower structure indicated by the reference numeral 21 in FIG. 2 is shown in blank parts of FIG. 11 . The reason why the holes are made around the corresponding electrodes is that this arrangement can prevent the pressure guide holes from being blocked when a side with a smaller pressure contacts the intermediate-layer movable diaphragm.

(6) The upper structure of the sensor (reference numerals 1, 3, 7, 35, 37, 39, 41, 43, and the upper portion of the upper metal bonding layer indicated by the reference numeral 5 shown in FIG. 2 ) is obtained by processing an SOI wafer, in which an upper silicon part of the SOI wafer is intrinsic silicon with a high resistivity, an intermediate layer of the SOI wafer is silicon oxide, and a lower silicon part of the SOI wafer is heavily doped silicon. The upper electrode 39 is derived from the heavily doped silicon of the lower silicon part of the SOI wafer. The reference numeral 37 refers to a lead pad of the upper electrode, which is used to connect the upper electrode 39 to an external circuit.

(7) The intermediate structure of the sensor is obtained by processing an SOI wafer, in which an upper silicon part of the SOI wafer is intrinsic silicon with a high resistivity, an intermediate layer of the SOI wafer is silicon oxide, and a lower silicon part of the SOI wafer is heavily doped silicon. The intermediate electrode 11 is derived from the heavily doped silicon of the lower silicon part of the SOI wafer. The reference numeral 29 refers to a lead pad of the intermediate electrode, which is used to connect the intermediate electrode 11 to the external circuit.

(8) The lower structure of the sensor is made of intrinsic silicon wafer with a high resistivity, the lower electrode is obtained through patterned doping on the SOI wafer, and a shape of a doped part is shown in the text description of FIG. 10 . A circular portion of the doped part will serve as a capacitor plate, a bottom rectangle portion of the doped part is used to make ohmic contact with the lead pad 25 of the lower electrode, and a portion between the circular portion and the bottom rectangle portion is a lead portion, which is responsible for realizing electrical connection between the circular portion and the bottom rectangle portion. By thermal oxidation and patterning an oxide layer, the lead portion doped with silicon is covered under a silicon dioxide layer, and the portion having the ohmic contact is exposed, as shown in FIG. 11 . The lead portion is covered with the silicon dioxide layer, therefore, the lower metal bonding layer 13 is prevented from being electrically connected with the lead portion when the metal eutectic bonding is adopted, thus realizing the electrical connection of the lead portion with an external metal solder joint through a side wall of the pressure cavity while ensuring the air tightness and a bonding strength of the pressure cavity.

(9) In order to ensure that the sensor can satisfy the three-stage change of the capacitors, a thickness of the intermediate-layer movable diaphragm (indicated by the reference numeral 43 in FIG. 2 ) can be selected from 0 to 10 μm, a ratio of the thickness to a diameter of the intermediate-layer movable diaphragm is greater than 1: 10, a spacing between the upper electrode 39 and the intermediate electrode 11 is in a range from 1 to 10 μm, and a spacing between the intermediate electrode 11 and the lower electrode 19 is in a range from 1 to 10 μm.

(10) The spacing between the lower electrode and the intermediate electrode is mainly composed of three parts including: silicon dioxide 27 having supporting and insulating functions on the lower surface of the intermediate structure, the lower metal bonding layer 13, and silicon dioxide 15 having supporting and insulating functions on the upper surface of the lower structure. A thickness of the silicon dioxide having supporting and insulating functions on the lower surface of the intermediate structure is in a range from 0 to 3 μm, a thickness of the lower metal bonding layer in a range from 0 to 4 μm, a thickness of the silicon dioxide having supporting and insulating functions on the upper surface of the lower structure in a range from 0 to 3 μm, a sum of the three thicknesses is no more than 10 μm, which just satisfies the requirements of the three-stage change of the capacitors of the sensor for small electrode spacing.

(11) The three electrodes of the sensor make the electric field lines (a potential change path) of the constant portions of the upper capacitor and the lower capacitor relatively longer (as shown in FIG. 1 ), and use the intrinsic silicon with the high resistivity (indicated by the reference numerals 3, 23 and 31 in FIG. 2 ) and silicon dioxide with a high resistivity and a relatively small dielectric constant (indicated by the reference numerals 15, 27 and 31 in FIG. 2 ), which makes the constant capacitors relatively small and a resistivity of the sensor greatly improved.

(12) The lead pads of the sensor are shown by the reference numerals 25, 29, 37 in FIG. 2 , the lead pad 37 is located in the upper structure, the lead pad 29 is located in the intermediate structure, the lead pad 25 is located in the lower structure, and the three lead pads are located in the three-layer structure respectively. Elevations of the three pads are different, and the three pads do not block each other, which can also be understood that the three lead pads are located on third steps, thus realizing that a leading operation can be performed from a direction perpendicular to the upper structure, which is convenient for the later packaging of the pressure difference sensor.

(13) The three layers of structures are formed together by the metal eutectic bonding. Compared with silicon-silicon direct bonding, the Aurum-Tin eutectic bonding or the copper-tin eutectic bonding process has much lower requirements on a bonding temperature, a pressure and a surface flatness. Further, compared with the anodic bonding process, the thermal stress problem caused by the mismatch of thermal expansion coefficients of materials is greatly reduced. Therefore, the metal eutectic bonding is more beneficial to realize the bonding of the complex three-layer structure and to manufacture the capacitive pressure difference sensor with three-layer structure.

Aiming at the design solution of the capacitive pressure difference sensor mentioned above, a corresponding process flow for manufacturing the capacitive pressure difference sensor is proposed. The specific processes used in the corresponding process flow are all existing mature processes, but for an MEMS device, it is often “one device, one process”, and the focus of innovation lies in the design of a process sequence. In terms of process flow, the pressure difference sensor designed in the present disclosure needs to process the wafers in which the upper, intermediate and lower structures are located respectively, then make the three-layer wafer become a whole through the metal eutectic bonding, and finally cut the three layers of wafers into separate sensors. Each specific process flow of the three-layer wafer will be described below.

1. A process flow of the upper structure (as shown in FIG. 4 )

Material Description: the upper structure is made of an SOI wafer, in which an upper silicon part of the SOI wafer is intrinsic silicon with a high resistivity, an intermediate layer of the SOI wafer is silicon oxide, and a lower silicon part of the SOI wafer is heavily doped silicon.

In step 1, a pressure guide hole (indicated by the reference numerical 1 in FIG. 2 ), a lead hole, an upper step hole, alignment marks and cutting marks located in the upper structure are etched. Specifically, the step 1 includes: cleaning the SOI wafer with alcohol, acetone and deionized water; Using a Hexamethyldisilazane (HMDS) oven to deposit tackifier on a surface of the SOI wafer to enhance adhesion of photoresist; coating the photoresist (positive adhesive) on an upper surface of the SOI wafer by spin coating; using the oven to pre-bake the photoresist on the upper surface for the first time; coating the photoresist (positive adhesive) on a lower surface of the SOI wafer by spin coating; using the oven to pre-bake the photoresist for the second time; exposing the photoresist on the upper surface, where an exposed portion includes the pressure guide hole, the lead hole, the upper step hole, the alignment marks and the cutting marks; using developer to expose etched parts; using the oven to post-bake the photoresist; using Tetramethyl ammonium hydroxide (TMAH) solution to wet etch the exposed portion until the silicon dioxide layer is reached; using the alcohol, the acetone, the deionized water and a Piranha solution to remove the photoresist.

In step 2, an etching process is performed on a lower surface of the SOI wafer to form a boss, so as to prepare for making the upper electrode (indicated by the reference numeral 39 in FIG. 2 ). Specifically, the step 2 includes: using the alcohol, the acetone and the deionized water to clean the SOI wafer; using the HDMS oven to deposit the tackifier on the surface of the SOI wafer to enhance adhesion of the photoresist; coating the photoresist (positive adhesive) on the lower surface of the SOI wafer by spin coating; using the oven to pre-bake the photoresist; exposing the photoresist on the lower surface to align with the alignment marks on the upper surface, where an exposed portion includes a region outside the boss and the alignment marks; using the oven to post-bake the photoresist; using an inductively coupled plasma (ICP) etching machine to dry etch the exposed portion until the silicon dioxide layer is reached; using the alcohol, the acetone, the deionized water and the Piranha solution to remove the photoresist.

In step 3, the exposed silicon dioxide layer after etching the lower surface is removed. Specifically, the step 3 includes: etching the exposed silicon dioxide layer using a buffered oxide etch (BOE) solution, and then cleaning the SOI wafer.

In step 4, an insulating silicon dioxide layer is formed on the surface of the SOI wafer, that is, silicon dioxide having an insulating function on the upper surface of the upper structure (indicated by the reference numeral 45 in FIG. 2 ) and silicon dioxide having supporting and insulating functions on the lower surface of the upper structure (indicated by the reference numeral 35 in FIG. 2 ). Specifically, the step 4 includes: performing dry thermal oxidation on the SOI wafer to generate an electrical insulation layer on a surface of the upper electrode. After processing, a top view of the upper surface of the upper structure is shown in FIG. 5 .

In step 5: the upper electrode (reference numeral 39 in FIG. 2 ) is exposed from the upper surface to prepare for a consequent lead. Specifically, the step 5 includes: using the alcohol, the acetone and the deionized water to clean the SOI wafer; using the HDMS oven to deposit tackifier on a surface of the SOI wafer to enhance adhesion of the photoresist; coating the photoresist (positive adhesive) on the lower surface of the SOI wafer using a glue sprayer; Using the oven to pre-bake the photoresist on the lower surface for the first time; coating the photoresist (positive adhesive) on the upper surface of the SOI wafer using the glue sprayer; using the oven to pre-bake the photoresist for the second time; exposing the photoresist on the upper surface, where an exposed portion includes a circular hole of a lead portion; using developer to expose the exposed portion; using the oven to post-bake the photoresist; using the BOE solution to wet etch the exposed portion until the silicon dioxide layer is reached; and using the alcohol, the acetone, the deionized water and the Piranha solution to remove the photoresist. The glue sprayer is chosen because the surface of the SOI wafer already has a through hole and a high-step structure, so spraying is chosen for the uniformity of glue application. After the processing is completed, the top view of the upper surface of the upper structure is shown in FIG. 5 .

In step 6, a process for preparing for manufacturing a portion of the upper metal bonding layer (indicated by the reference numeral 5 in FIG. 2 ) located in the upper structure is performed. The upper wafer is coated with the photoresist by a glue spraying process, and then exposed, developed and post-baked in sequence after drying, so that a non-bonded region is covered with the photoresist.

In step 7, a process for manufacturing the portion of the upper metal bonding layer (indicated by the reference numeral 5 in FIG. 2 ) located in the upper structure. Specifically, the step 7 includes: performing metal sputtering on the lower surface of the SOI wafer, and Titanium (Ti), Nickel (Ni) and aurum (Au) are sputtered on the lower surface in turn. The sputtering of the lower surface is for forming the upper metal bonding layer (indicated by the reference numeral 5 in FIG. 2 ) together with a metal layer of the intermediate structure. The upper structure can be obtained by using a Lift-off process to complete metal patterning and then annealing. After processing, the top view of the upper surface of the upper structure is shown in FIG. 5 , and a top view of the lower surface is shown in FIG. 6 .

2. A process flow of the intermediate structure (as shown in FIG. 7 )

In step 1, silicon dioxide is formed on a surface of the intermediate structure to prepare for the formation of silicon dioxide 27 having supporting and insulating functions on the lower surface of the intermediate structure and silicon dioxide 33 having supporting and insulating functions on the upper surface of an intermediate structure; and to prepare for the formation of a portion of the upper metal bonding layer 5 located in the intermediate structure, a portion of the lower metal bonding layer 13 located in the intermediate structure, and the lead pad 25 of the lower electrode. Firstly, wet thermal oxidation is performed on a surface of an SOI wafer to form a thick oxide layer. Then, upper and lower surfaces of the SOI wafer are coated with photoresist, exposed and developed. After that, metal sputtering is performed, including sputtering metal such as Ti, Ni, Au, Tin (Sn) and Au in turn, and the photoresist is stripped by a Lift-off process to complete metal patterning.

In step 2, silicon dioxide on a surface of a portion to be etched is removed. The SOI wafer (silicon wafer) is coated with the photoresist, exposed, and then developed on both sides thereof to expose the silicon dioxide corresponding to a cutting hole and the intermediate-layer movable diaphragm. A BOE solution is used to etch the exposed silicon dioxide. After that, an acetone solution is used to dissolve the photoresist.

In step 3, the cutting hole and the intermediate-layer movable diaphragm are formed. The SOI wafer is coated with photoresist, exposed and developed on both sides thereof, and then the upper and lower surfaces of the SOI wafer are etched successively until a silicon dioxide layer in the middle of the SOI wafer is reached.

In step 4, the photoresist is removed. After the etching is completed, because the intermediate-layer movable diaphragm has been formed and the intermediate-layer movable diaphragm is thin, when acetone is used to remove the photoresist, if the SOI wafer is directly taken out of the acetone, a surface tension of the acetone will break the intermediate-layer movable diaphragm, so it is not possible to take the wafer directly from the acetone. As such, the acetone can be diluted continuously by adding alcohol and then deionized water, and the acetone can be heated at the same time to accelerate volatilization. Finally, after the acetone is volatilized, the SOI wafer can be taken out.

3. A process flow of the lower structure (as shown in FIG. 9 )

In step 1, the lower electrode (indicated by the reference numeral 19 in FIG. 2 ) is formed. Firstly, upper and lower surfaces of an intrinsic silicon wafer are coated with photoresist, exposed, developed, etched and degummed to form alignment marks of the intrinsic silicon wafer. Patterned ion implantation is performed on an upper surface of the intrinsic silicon wafer, and a process design with a high dose and a high voltage is selected during the patterned ion implantation. Shapes of the lower electrode and a lead portion thereof are shown in FIG. 10 .

In step 2, silicon dioxide on a surface of the lower structure is formed to prepare for the subsequent processing, and a roughness of the surface is reduced and a flatness of the surface is improved at the same time. Wet thermal oxidation is performed on an upper surface of a matrix (the intrinsic silicon wafer). The reason why the wet thermal oxidation is selected is that an oxide layer generated by the wet thermal oxidation is thicker and the quality of the oxide layer is good in all aspects. Then, a planarization operation is performed. The reason why the planarization operation is selected is that a growth rate of an oxide layer in a doped part is higher than that in an intrinsic silicon part during the oxidation process, therefore, considering the later bonding operation, the planarization operation is used to improve the flatness.

In step 3, pressure guide holes (indicated by the reference numeral 21 in FIG. 2 ) in the lower structure are formed and the lower electrode is exposed. Both surfaces of the matrix (the intrinsic silicon wafer) are coated with photoresist by spin coating, and metal patterning of the photoresist is completed. A region corresponding to the lower electrode is exposed from an upper surface of the matrix, and a region corresponding to the pressure guide holes is exposed from a lower surface of the matrix. Firstly, A BOE solution is used to etch silicon dioxide exposed from the upper surface and the lower surface, and then the lower surface is dry etched to complete the manufacture of the pressure guide holes (indicated by the reference numeral 21 in FIG. 2 ) of the lower structure. The residual photoresist is removed.

In step 4, a silicon dioxide insulation layer (indicated by the reference numeral 17 in FIG. 2 ) on an exposed surface of the lower electrode is formed. Dry thermal oxidation is performed.

In step 5, doped silicon under the lead pad (indicated by the reference numeral 25 in FIG. 2 ) of the lower electrode is exposed. An upper surface of the lower wafer is coated with glue. A glue spraying manner is selected because of the existence of through holes. After exposure and development, a BOE solution is used to etch the exposed silicon dioxide to prepare for the manufacture of the lead pad (indicated by the reference numeral 25 in FIG. 2 ) of the lower electrode.

In step 6, metal sputtering is performed to prepare for the formation of a portion of the lower metal bonding layer (indicated by the reference numeral 13 in FIG. 2 ) located in the lower structure and the lead pad (indicated by the reference numeral 25 in FIG. 2 ) of the lower electrode. The upper surface of the matrix is coated with the photoresist again. Because the matrix has a through-hole structure, the gluing manner is spraying. After the patterning of the photoresist is completed, Ti, Ni and Au are sputtered to complete the manufacture of metal needed by the lower metal bonding layer in the lower structure and metal needed by the lead pad.

In step 7, the portion of the lower metal bonding layer (indicated by the reference numeral 13 in FIG. 2 ) located in the lower structure and the lead pad (indicated by the reference numeral 25 in FIG. 2 ) of the lower electrode are formed. The Lift-off process is performed to complete metal patterning.

Under an environmental condition of a certain temperature and a pressure, metal eutectic bonding is performed on the three-layer wafer, and the obtained structure is shown in FIG. 13 .

After the eutectic bonding is completed, the lead pad (indicated by the reference numeral 37 in FIG. 2 ) of the upper electrode and the lead pad (indicated by the reference numeral 29 in FIG. 2 ) of the intermediate electrode are manufactured. The three bonded-layer wafer is covered with a sputter mask and is aligned. After that, Ti, Ni and Au are sputtered in turn to complete the manufacture of the lead pads. The manufacturing schematic view is shown in FIG. 14 .

Cutting is then performed. Because dust will be generated during the cutting and enter the cavity through the pressure guide hole, a peeling photosensitive dry film is used to cover the upper and lower surfaces of three bonded-layer wafer first. After cutting, exposure is performed, and then r the peeling photosensitive dry film is removed to complete the manufacture of the overall structure. The schematic view of the cutting process is shown in FIG. 15 .

After the cutting is completed, an independent pressure difference sensor structure can be obtained, a top view of which is shown in FIG. 16 .

Second Embodiment

A design method of an MEMS contact capacitive pressure difference sensor includes the following steps.

(1) For a patterned constant electrode and its lead circuit prepared by doping process, ion implantation is used to complete deep doping of a high dose and a high voltage for the electrode. After that, wet oxidation and planarization of a silicon wafer are completed, and a silicon oxide layer is partially corroded to expose a patterned part of the electrode. The reason for the planarization operation is that an oxidation rate of a doped part is too high, resulting in a surface of the silicon oxide layer of the doped part being slightly higher than that of an undoped part, and a flatness of the whole wafer exceeds the requirement for the bonding.

(2) Upper, intermediate and lower layers of bonded silicon wafers are etched and cut to form grooves respectively, and sensor areas of the three bonded silicon wafers have a same width, and a length increases from top to bottom of the three bonded silicon wafers by tens to hundreds of microns. After covering the pressure guide hole with a mask (e.g. white film), the sensor is cut into a rectangle and form a three-layer lead step (as shown in FIG. 13 ).

In terms of a process flow, the pressure difference sensor designed in the present disclosure needs to first process the upper, intermediate and lower three-layer structures respectively, then perform metal eutectic bonding on the three-layer structures, and finally a cutting process is performed to obtain separated sensors.

The basic principle, main features and advantages of the present disclosure have been shown and described above. It should be understood by those skilled in the art that the present disclosure is not limited by the above-mentioned embodiments, but the above-mentioned embodiments and descriptions are merely used to describe the principles of the present disclosure, and various changes and improvements in the present disclosure without departing from the spirit and scope of the present disclosure can be obtained, which fall within the scope of protection of the present disclosure. The scope of protection claimed by the present disclosure is defined by the appended claims and their equivalents. 

What is claimed is:
 1. A pressure difference sensor, manufactured by a manner of bonding three layers of wafers, and comprising: an upper structure, an intermediate structure and a lower structure; wherein each of the upper structure and the intermediate structure is manufactured by a silicon-on-insulator (SOI) wafer, and the lower structure is manufactured by patterned doped intrinsic silicon; wherein an upper electrode, an intermediate electrode and a lower electrode are respectively arranged on the upper structure, the middle structure and the lower structure, and a lead pad of each of the upper electrode, the intermediate electrode and the lower electrode is located on a corresponding one of three-stepped steps at a side of the pressure difference sensor; wherein annular through holes are formed around the upper electrode and the lower electrode; the pressure difference sensor is made by cutting the three layers of wafers after bonding of the three layers of wafers, and a manner of the bonding is metal eutectic bonding; wherein the metal eutectic bonding comprises an upper metal bonding layer and a lower metal bonding layer, an upper portion of the upper metal bonding layer comes from an upper wafer and a lower portion of the upper metal bonding layer comes from an intermediate wafer; and an upper portion of the lower metal bonding layer comes from an intermediate wafer and a lower portion of the lower metal bonding layer comes from a lower wafer; wherein the upper electrode is located in the upper structure, and is formed by processing the upper wafer; the intermediate electrode is located in the intermediate layer structure, and is formed by processing the intermediate wafer; the lower electrode is located in the lower structure; wherein a pressure guide hole in the upper structure and a pressure guide hole in the lower structure are arranged to be surround the upper electrode and the lower electrode respectively; wherein the upper structure is made by processing the SOI wafer, an upper silicon part of the SOI wafer is intrinsic silicon with a high resistivity, an intermediate layer of the SOI wafer is silicon oxide, a lower silicon part of the SOI wafer is heavily doped silicon, and the upper electrode is derived from the heavily doped silicon of the lower silicon part of the SOI wafer; wherein the intermediate structure is made by processing the SOI wafer, an upper silicon part of the SOI wafer is intrinsic silicon with a high resistivity, an intermediate layer of the SOI wafer is silicon oxide, a lower silicon part of the SOI wafer is heavily doped silicon, and the intermediate electrode is derived from the heavily doped silicon of the lower silicon part of the SOI wafer; and the lead pad of the intermediate electrode is configured to connect the intermediate electrode to an external circuit; wherein the lower structure is made by processing an intrinsic silicon wafer with a high resistivity, the lower electrode is made through patterned doping of the wafer, a circular portion of a doped part mainly plays the role of a capacitor plate, a bottom rectangle portion of the doped part is configured to make ohmic contact with the lead pad of the lower electrode, and a portion between the circular portion and the bottom rectangle portion is a lead portion, which is responsible for realizing the electrical connection between the circular portion and the bottom rectangle portion; wherein a spacing between the lower electrode and the intermediate electrode is composed of three parts comprising: silicon dioxide having supporting and insulating functions on a lower surface of the intermediate structure, the lower metal bonding layer, and silicon dioxide having supporting and insulating functions on an upper surface of the lower structure; and wherein a thickness of the silicon dioxide having supporting and insulating functions on the lower surface of the intermediate structure is in a range from 0 to 3 μm, a thickness of the lower metal bonding layer is in a range from 0 to 4 μm, a thickness of the silicon dioxide having supporting and insulating functions on the upper surface of the lower structure is in a range from 0 to 3 μm, and a sum of the three thicknesses is no more than 10 μm.
 2. A manufacturing method of a sensor comprising the pressure difference sensor according to claim 1, wherein the method comprises process flows for manufacturing the upper structure, the intermediate structure and the lower structure; wherein the process flow for manufacturing the upper structure comprises: step 1, etching the pressure guide hole, a lead hole, an upper step hole, aligning marks and cutting marks located in the upper structure; step 2, performing etching a lower surface to form a boss to prepare for manufacturing the upper electrode; step 3, removing a silicon dioxide layer exposed after etching the lower surface; step 4, forming an insulating silicon dioxide layer on a surface of the wafer, that is, the silicon dioxide having supporting and insulating functions on the lower surface of the intermediate structure, and the silicon dioxide having supporting and insulating functions on the upper surface of the lower structure; step 5, exposing the upper electrode on the upper surface to prepare for a consequent lead; step 6, preparing for manufacturing a portion of the upper metal bonding layer located in the upper structure; and step 7, manufacturing the portion of the upper metal bonding layer located in the upper structure; wherein the process flow for manufacturing the intermediate structure comprises: step 1, forming silicon dioxide on a surface to: prepare for forming silicon dioxide having supporting and insulating functions on the lower surface of the intermediate structure and silicon dioxide having supporting and insulating functions on the upper surface of an intermediate structure; and prepare for forming a portion of the upper metal bonding layer located in the intermediate structure, a portion of the lower metal bonding layer located in the intermediate structure, and the lead pad of the lower electrode; step 2, removing silicon dioxide on a surface of a portion to be etched; step 3, forming a cutting hole and the intermediate-layer movable diaphragm; and step 4, removing the photoresist; wherein the process flow for manufacturing the lower structure comprises: step 1: forming the lower electrode; step 2: forming silicon dioxide on a surface of the lower structure to prepare for the subsequent processing, and reducing a roughness of the surface and improving a flatness of the surface; step 3: forming the pressure guide hole in the lower structure to expose the lower electrode; step 4, forming a silicon dioxide insulating layer on an exposed surface of the lower electrode; step 5, exposing doped silicon under the lead pad of the lower electrode; step 6, sputtering metal to prepare for forming a portion of the lower metal bonding layer located in the lower structure and the lead pad of the lower electrode; and step 7: forming a portion of the lower metal bonding layer located in the lower surface and the lead pad 25 of the lower electrode.
 3. A design method of a Micro-Electro-Mechanical Systems (MEMS) contact capacitive pressure difference sensor comprising the pressure difference sensor according to claim 1, and the method comprising: (1) for a patterned constant electrode and a lead circuit thereof manufactured by a doping process, using ion implantation used to complete deep doping of a high dose and a high voltage for the electrode; after that, completing wet oxidation and planarization of a silicon wafer, and partially corroding a silicon oxide layer to expose a patterned part of the electrode; wherein the reason for the planarization operation is that an oxidation rate of a doped part is higher, resulting in a surface of the silicon oxide layer of the doped part being slightly higher than that of an undoped part, and a flatness of the whole wafer exceeds the requirement for the bonding; and (2) etching and cutting upper, intermediate and lower layers of bonded silicon wafers to form grooves respectively, wherein sensor areas of the three bonded silicon wafers have a same width, and a length increases from top to bottom of the three bonded silicon wafers by tens to hundreds of microns; and after covering the pressure guide hole with a mask, cutting the sensor into a rectangle and form a three-layer lead step.
 4. A signal acquisition circuit comprising a pressure difference sensor including the pressure difference sensor according to claim
 1. 